NXP Semiconductors /MIMXRT1021 /DMA0 /TCD15_CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TCD15_CSR

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NO_START)START 0 (DISABLED)INTMAJOR 0 (DISABLED)INTHALF 0 (NO_CLEAR)DREQ 0 (NORMAL)ESG 0 (DISABLED)MAJORELINK 0 (ACTIVE)ACTIVE 0 (DONE)DONE 0MAJORLINKCH 0 (DISABLED)BWC

INTMAJOR=DISABLED, BWC=DISABLED, MAJORELINK=DISABLED, INTHALF=DISABLED, START=NO_START, ESG=NORMAL, DREQ=NO_CLEAR

Description

TCD Control and Status

Fields

START

Channel Start

0 (NO_START): Channel is not explicitly started

1 (START): Channel is explicitly started via a software initiated service request

INTMAJOR

Enable an interrupt when major iteration count completes.

0 (DISABLED): End of major loop interrupt is disabled

1 (ENABLED): End of major loop interrupt is enabled

INTHALF

Enable an interrupt when major counter is half complete.

0 (DISABLED): Half-point interrupt is disabled

1 (ENABLED): Half-point interrupt is enabled

DREQ

Disable Request

0 (NO_CLEAR): The channel’s ERQ field is not affected

1 (CLEAR): The channel’s ERQ field value changes to 0 when the major loop is complete

ESG

Enable Scatter/Gather Processing

0 (NORMAL): The current channel’s TCD is normal format

1 (SCATTER): The current channel’s TCD specifies a scatter gather format

MAJORELINK

Enable channel-to-channel linking on major loop complete

0 (DISABLED): Channel-to-channel linking is disabled

1 (ENABLED): Channel-to-channel linking is enabled

ACTIVE

Channel Active

DONE

Channel Done

MAJORLINKCH

Major Loop Link Channel Number

BWC

Bandwidth Control

0 (DISABLED): No eDMA engine stalls

2 (STALL4): eDMA engine stalls for 4 cycles after each R/W

3 (STALL8): eDMA engine stalls for 8 cycles after each R/W

Links

() ()